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TERATEC 2025 Forum The European meeting for Experts in High Power Digital Simulation . HPC/HPDA . Artificial Intelligence . Quantum Computing

Thursday May 22 Workshop 06 - 9:30 am to 11:30 am

Components and increasing performances of HPC systems: effervescence, divergence, convergence
Chaired by Marc Duranton, Research Fellow, CEA and Denis Dutoit, Program Manager,Advanced Computing, CEA

AMD Multi-die Architecture for Exa-Class HPC and AI Systems
By Jose Noudohouenou, Senior Staff Software Engineer, AMD

Traditional monolithic silicon design and manufacturing faces various challenges that include increasing cost and complexity. One solution consists in breaking up the monolithic silicon into smaller and specialized functions called chiplets, which are then co-packaged to create larger, more complex semiconductor devices. These small and modular integrated circuits consist of a highly tuned and complex building block or a discrete group of functions that allow for SoC differentiation. Via co-packaging, chiplets provide designers and manufacturers with flexible and scalable design capabilities to meet the design requirements of modern SoCs. At AMD, challenges and limitations of traditional monolithic design have been addressed by designing and manufacturing chiplet-based System on Chip (SoC) solutions leading to exascale class accelerated supercomputers for both HPC and AI. In this presentation, we will talk about AMD multi-die architecture and the benefits of adopting such a design approach. Furthermore, we will discuss the future of high computing systems since nowadays, HPC is increasingly influenced by AI.

Biography: José Noudohouenou obtained his PhD from the University of Versailles in 2013 and specialises in application characterisation, code optimisation and performance prediction. He then worked at Exascale Computing Research Lab (France) as a post-doctoral researcher focusing on HW/SW codesign, classification and codelet equivalence issues. While optimising scientific applications, José accepted a position at Intel Corporation (USA), and later at Intel Federal where he was involved in various US projects including porting and optimising HPC applications on Intel GPUs. Subsequently, José joined AMD in 2021 and continues to optimise both HPC and AI applications on AMD GPUs while he is responsible for AMD's Centre of Excellence for the Adastra machine at CINES in Montpellier, France.

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