European Approach Towards Energy Efficient High Performance

The third phase of the Mont-Blanc project brings together a renewed set of partners including industrial technology providers and academic research centres from 6 European countries to design energy efficient HPC solutions

Back in October 2011, the Mont-Blanc consortium launched the first phase of a project aimed at exploring an energy-efficient alternative to current supercomputers, based on low-power mobile processors, with the ambition of setting future HPC standards for the Exascale era. Four years later, the Mont-Blanc project has indeed given birth to a fully functional prototype that allowed project members to demonstrate the viability of using European embedded commodity technology for High Performance Computing. The project also defined a set of developer tools and ported real scientific applications to this new environment. More globally, the project has given good visibility to the concept of using mobile technology for HPC.

Today, energy efficiency is more than ever the primary concern for future Exascale systems, which confirms the relevance of the Mont-Blanc approach.  The objective of the third phase of the Mont-Blanc project is to leverage the lessons learned during the first and second phases of the initiative. The project will continue to take a holistic approach, encompassing hardware, operating system and tools, and applications, with the following targets:

• Defining the architecture of an Exascale-class compute node based on the ARM architecture, and capable of being manufactured at industrial scale;

• Assessing the available options for maximum compute efficiency;

• Developing the matching software ecosystem to pave the way for market acceptance of ARM solutions.

The third phase of the Mont-Blanc project is coordinated by Bull, the Atos brand for technology products and software, and has a budget of 7.9 million Euros, funded by the European Commission under the Horizon2020 program. It was launched on 14th October at the University of Versailles Saint-Quentin-en-Yvelines with a kick-off meeting that gathered representatives of all partners.

Within a few years from now, supercomputers are expected to reach the Exaflops (1018 Floating point operations per second) levels of performance within a power budget of 20MW. This implies that energy efficiency must increase by a factor of 10, compared to the most efficient current supercomputers. Scaling of current technologies will not be enough to meet this target.

“Power consumption is a major hurdle in the race to Exascale, and the path explored by Mont-Blanc is extremely promising. Mobile chips have very low power consumption, and previous Mont-Blanc projects proved that they are capable of sustaining HPC workloads, with a small loss of performance largely compensated by increased cost efficiency. We are confident that mobile commodity technologies can be leveraged for scientific computation, and will be at the heart of some of the first exascale supercomputers” says Etienne Walter, new coordinator of the Mont-Blanc 3 project.

The third phase of the Mont-Blanc project is run by a purely European consortium that includes:

• Industrial hardware/software technology providers: Bull, the leading European HPC manufacturer (France), ARM, the world leader in embedded high-performance processors (United Kingdom), and AVL, the world's largest independent company for the development, simulation and testing technology of powertrains (Austria);

• Academic/research HPC centres: Barcelona Supercomputing Centre (Spain), Swiss Federal Institute of Technology in Zurich (Switzerland), CNRS (CNRS/LIRMM - France), University of Stuttgart (HLRS -Germany), University of Cantabria (Spain), University of Graz (Austria), University of Versailles Saint Quentin (France).

This project has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No 671697.

Pour plus d’information :

Bull/Atos – Etienne Walter
Tel: +33 1 30 80 74 96 - Email