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TERATEC 2017 Forum
Workshop 7 - Wednesday, June 28 - from 14:00 to 17:30

Chaired by Guillaume COLIN DE VERDIERE, CEA

During the past years we have witnessed the convergence between HPC and Big Data (BD), now named HPDA. Both worlds are centered on data movement. When HPC is producing large simulation results, BD is shuffling large data bases. To meet both cases, vendors are trying to offer the best solutions to minimize the cost of data movement be it internally between functional units or externally between compute nodes of a cluster.

This session was the opportunity to survey the latest developments in terms of interconnects through presentations from major actors in this field.

With the participation of :

Scalability ot the CRAY XC and its ARIES network.
Tony FORD, Director of Engineering, European HPC Systems R&D, CRAY Inc.

Abstract & Bio Download the presentation

The GEN-Z Consortium
Patrick DEMICHEL, Distinguished Technologist, HPE

Abstract & Bio Download the presentation

Intel® Omni-Path Architecture: The Path To Exascale
John SWINBURNE, HPC Technical Specialist, INTEL

Abstract & Bio Download the presentation

Maximising heterogeneous system performance with ARM Interconnect and CCIX technologies
Neil PARRIS, Directeur Marketing Interconnect, ARM

Abstract & Bio Download the presentation

Steve FIELDS, IBM Fellow, Chief Engineer of Power Systems, IBM SYSTEMS & TECHNOLOGY Group

Abstract & Bio Download the presentation

Boost HPC application performance thanks to hardware offload
Fabien LOCUSSOL, Interconnect Product Manager, ATOS

Abstract & Bio Download the presentation

Next Generation of Co-Processors Emerges – In-Network Computing

Abstract & Bio Download the presentation

© TERATEC 2017

For any other information regarding the workshops, please contact :

Jean-Pascal JEGU
Tel : +33 (0)9 70 65 02 10
2, rue de la Piquetterie


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