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Teratec HPC Hackathon 2025

Industrial codes optimization

Principles

Our goal with this hackathon is to unite Master II-level HPC students in a virtual competition focused on computational codes provided by industrial users.

This virtual competition will rely on Amazon Web Services (AWS) instances based on ARM technologies. Indeed, the target architectures (AWS Graviton 4) offer certain approaches (software ecosystem, design) that motivate a specific effort compared to traditional Intel or AMD type architectures. Typically, on the Graviton 4 processor, we can mention the use of SIMD units (Scalable Vector Extension/SVE2 compared to AVX2 or AVX-512 on x86 architectures) or the availability of 12 DDR5 memory channels.

This hackathon is structured around computational codes, software environments and hardware solutions that have already been tested by industry. The compilation recipes and optimization phases have been validated before the event. The students will therefore be in a framework close to a guided practical session with the opportunity to increase their understanding of industrial issues around high- performance simulation. No specific contributions from students in terms of porting or optimization are expected (these codes are largely proven in a production context and on multiple hardware architectures). The participants will nevertheless be credited by the industrial partners (the codes have an open status) in case of significant advances.

Details

Students are encouraged to take an iterative approach to porting and optimizing these industrial codes/kernels. The latter are of different nature/complexity and will allow the deployment of the classical phases of taking control of a scientific application. The evaluation of the teams (4 students maximum per team) will be based on the following points:

• Porting: it will be a question of validating the application on Arm architectures (Graviton2/Graviton3) by focusing on the test case provided by the industrial partner. The validation will be done by comparing the result files and/or by comparing the results on different platforms (x86/Arm).

• Profiling: Students will be asked to use classical application profiling tools to identify performance locks... this will include identifying the hotspots of these applications (compiler report, dynamic code analysis...)
• Advanced optimization: During this phase, the students will be able to make some modifications to the codes in order to improve the performances. For small applications (e.g., CGG code, this may involve adding OpenMP directives or modifying the organization of loops...). In the case of complex code, participants can focus on the impact of the different compilation chains and work on extracting some kernels (mini-apps). The latter could then be the subject of specific efforts.
  

- Arm, Nvidia and GNU compilers will be available during the hackathon. Students will also have access to various code profiling tools.

- The synthesis of the obtained results (compilation recipes, validation procedure, optimization, loops extraction ...) will be made available on a Git repository in order to facilitate the evaluation and the reproducibility.

Proposed codes / Identified Kernels (September 2024)

EDF: Code_Aster

Code_Aster reconciles the following two objectives:

·       Providing a reliable, robust, and high-performance simulation software for engineering studies, within a framework of development and distribution under quality assurance.
·       Accommodating and capitalizing on numerical mechanics models developed by EDF's R&D.

Constantly developed, maintained, and enriched with new models, Code_Aster contains over one million lines of source code, mostly in Fortran and Python.
In addition to the standard features of thermo-mechanical simulation software, Code_Aster is particularly rich in constitutive laws, finite elements, and load types. Its area of excellence lies in non-linear simulations, particularly in the fields of civil engineering, fracture mechanics, and geo-materials.

VIRIDIEN (CGG): Code Serial

The Serial code developed by Viridien is a Monte Carlo-type code with ample opportunities for optimization, including parallelization and vectorization, validated on ARM systems. This code offers developers significant flexibility for transformations, including the choice of a random number generator, which can be optimized to improve numerical convergence and performance.

The code reflects real industrial applications, where entire clusters are used for similar computations, but it has been adapted to showcase a wide range of problems and solutions, from small to long runs. This flexibility will allow teams to demonstrate various levels of skill in optimizing the code, leading to potential differences in outcomes.

Format

Timeline :

1. Online registration for teams of 4 students: Deadline November 20, 2024!

   Webinar Presentation: on Friday, December 13, 2024, from 4 PM to 6 PM. Presentation of the hackathon, the partners and the interest of the codes to be used + Q/A. The webinar will be recorded and available on Teratec's website all year

2. Hackathon from Monday, January 20, 2025, 9 AM to Monday, January 27, 2025, 9 AM.

1. The work can be distributed according to the teams' preferences over the 5 days of the competition.
2. Machine access and technical support from AWS, ARM and UCit will be available from Monday, January 20, 2025, 9 AM to Friday, January 25, 2025, 7 PM
3. The award ceremony and feedback from students during the Teratec Forum 2025

Prizes

As in previous editions, the competition will include a ranking. The winning team will be awarded 4 MacBooks.

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