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Home > TERATEC FORUM > Cafe_Europeen_Recherche
European Research Café
An all new area dedicated to European research projects and initiatives in the fields of digital simulation, HPC, and Big Data.
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COLOC |
Presentation : The evolution of HPC infrastructures implies a far better management of data locality to minimize data access time and data transfer costs across the various processors. This is the reason why the COLOC project is designing and developing methods and tools to model all compute and network resources of an HPC infrastructure (as a hierarchical topology), as well as associated services enabling to optimize the process and data placement using the topology and inter-process data flow information. More precisely, the COLOC project aims at (i) developing methods and tools enabling to model all resources of a computing platform using a hierarchical topology that describes the characteristics of these resources, (ii) profiling applications, and (iii) enhancing upper software layers (resource manager such as SLURM; data communication libraries such as MPI; performance analysis tools such as MAQAO) and applications as well to better manage data placement. The HWLOC & NETLOC modeling tool is being developed by INRIA while UVSQ is enhancing its MAQAO technology for detailed performance analysis. Furthermore, the Scilab environment and the FOISOL solver are also adapted to benefit from this optimal data placement mechanism while the validation is being made by industrial partners (Dassault Aviation and ESI/Efield) with compute intensive applications in different domains: CFD (Computational Fluid Dynamics), CEM (Computational Electromagnetics) and CSM (Computational Structural Mechanics). |
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EXDCI |
EXDCI objective is to coordinate the development and implementation of a common strategy for the European HPC Ecosystem. The two most significant HPC bodies in Europe, PRACE and ETP4HPC, join their expertise in this 30-months project with a budget of € 2.5 million, starting from September 2015. EXDCI aims to support the road-mapping, strategy-making and performance-monitoring activities of the ecosystem, i.e.:
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Presentation : The FIPS project aims to significantly increase energy-efficiency of supercomputers, thus opening them up to a wide range of new applications and users. With the RECS|Box System, a highly scalable heterogeneous hardware platform is developed, which seamlessly integrates CPUs (general purpose and embedded ones), Field Programmable Gate Arrays (FPGAs), GPUs and many-core processors. To ease programming of the platform, FiPS is setting up a programming methodology, simplifying the usage of the heterogeneous computing devices as processing elements in a holistic integrated hardware and software server eco-system. The main goal of the project is to develop a new class of low-power TCO-optimised appliances with built-in efficiency and dependability enhancements. The appliances will be easy to integrate with a broad ecosystem of management software and fully software-defined to enable optimisation for a variety of future demanding applications in a cost-effective way. The M2DC flexible server architecture with heterogeneous hardware including ARM CPUs and FPGAs will enable customisation and smooth adaptation to various types of data centres, while advanced management strategies and system efficiency enhancements (SEE) will be used to achieve high levels of energy efficiency, performance, security and reliability. |
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MONT-BLANC 3 |
The third phase of the Mont-Blanc project brings together a renewed set of partners to design a high-end HPC platform based on ARM processors, as well as the matching software ecosystem. Back in October 2011, the Mont-Blanc consortium launched the first phase of a project aimed at exploring an energy-efficient alternative to current supercomputers, based on low-power mobile processors, with the ambition of setting future HPC standards for the Exascale era. Five years later, the Mont-Blanc fully functional prototype allowed project members to demonstrate the viability of using European embedded commodity technology for HPC. The project also defined a set of developer tools and ported real scientific applications to this new environment. The third phase of the Mont-Blanc project will continue to take a holistic approach, encompassing hardware, operating system and tools, and applications. |
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POP |
The growing complexity and heterogeneity of modern HPC infrastructures implies the refactoring of the code of compute intensive applications so that they can fully exploit the power of such infrastructures. However, code refactoring is not an easy task: it requires powerful performance analysis tools and experts. This is why the POP (Performance Optimization and Productivity) CoE (Center of Excellence) has been created with the goal to provide – for free - a precise understanding of application and system behavior as well as suggestion/support on how to refactor code in the most productive way. These services are offered to any organization (e.g. industry, research center, university) and can be used for open source as well as proprietary code. If needed, the POP experts can also build a PoC (Proof-of-Concept) to demonstrate the efficiency of a given type of code modification on a representative module of the application code. The resulting performance increase should enable research and industry to be more productive (shorter time-to-solution, reduction of energy consumption, ...) and more competitive (better results).
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More information about the sponsoring and the reservation of a booth in the exhibition, please contact :
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