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TERATEC 2025 Forum The European meeting for Experts in High Power Digital Simulation . HPC/HPDA . Artificial Intelligence . Quantum Computing

Thursday May 22 Workshop 06 - 9:30 am to 11:30 am

Components and increasing performances of HPC systems: effervescence, divergence, convergence
Chaired by Marc Duranton, Research Fellow, CEA and Denis Dutoit, Program Manager,Advanced Computing, CEA

The current trends for the HPC elements
By Marc Duranton, Research Fellow, CEA and Denis Dutoit, Program Manager,Advanced Computing, CEA

Biography: Dr. Marc Duranton is Senior Fellow of CEA and member of the Digital Systems and Integrated Circuits Division of CEA, where he is involved in realizations (hardware accelerators and software tools) for Artificial Intelligence, for Cyber Physical Systems and for distributed systems from IoT to HPC. He previously worked in Philips and NXP where he led the development of the family of L-Neuro chips, digital processors using artificial neural networks and on several video coprocessors for the VLIW processor TriMedia. His interests include High Performance Computing, Deep Learning, distributed and embedded Artificial Intelligence systems, emerging paradigms for computing systems, distributed and federated computing, models of computation and communication with time guaranties. He is in charge of the roadmap activities of the HiPEAC community ( https://www.hipeac.net/vision/ ) and is involved in the Strategic Research and Innovation Agenda of the Electronics Components and Systems (ECS SRIA) and in the SRA of the European Technology Platform for High Performance Computing (ETP4HPC SRA).

Biography: Denis Dutoit is senior program manager for advanced computing and digital architectures at CEA-List, one of the world’s largest organizations for research in digital architectures and system integration. He coordinated the European ExaNoDe project that developed a computer node demonstrator combining chiplets, an active interposer, and bare dies in a System-in-Package (SiP). He has also contributed to the architecture of the European Processor Initiative (EPI). His current focus is on architecture pathfinding into chiplet-based designs for intensive computing systems. Before joining CEA, he was a system-on-chip architect at ST Microelectronics and ST Ericsson. He has authored or coauthored more than 20 articles, including invited talks and tutorials at IEEE conferences.  He earned a PhD in signal processing from Telecom Paris (ENST).

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